If you look at the timing diagrams in the PIC data sheets (I'm 
looking at the PIC18F4520) titled "I2C Slave Mode Timing with SEN=1", 
it shows that the clock is held low AFTER the acknowledge. It shows 
CKP goes low after the ninth clock, and stays low until CKP is set in 
software, which allows the master to drive the clock high again.

Steve Rapinchuk

Alan B. Pearce  says:
>
>  The I2C spec is not explicit about when clock stretching can occur.
>I thought it was pretty explicit, at the time I looked at it.
>It implies that it is done by a slave after a the slave sends an 
>acknowledge, which is how Microchip implements it in PICs by using 
>the CKP bit.
>Umm, it really does it at (or during) the time of sending the ACK 
>bit, not after.
>And that is how the MChip devices do it (although some have found 
>problems with 16F88 IIRC). The slave device holds the CLK low during 
>the ACK bit time so that it doesn't go high when the master allows 
>it to go high, resulting in the stretched clock bit.
>Technically I think you can have a slave device do this on every 
>clock bit if it cannot clock the data fast enough, but I personally 
>don't know of any devices that do this. This may be the area where 
>you feel the spec is not explicit.
>


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