I have seen devices that support bit-level (any bit) clock stretching.

David
www.dajac.com


> I'm considering a project which requires extending an I2C bus over a
> UART, but I'm not sure this is possible. The setup would look
> something like this:
>
> MASTER <=I2C=> PIC1 <=UART=> PIC2 <=I2C=> SLAVE
>
> 1. A MASTER I2C device sends an I2C start condition.
> 2. PIC1 (configured as an I2C slave) receives the start and sends a
> START command over the UART to PIC2.
> 3. PIC2 (configured as an I2C master), receives a START over the UART
> and sends a I2C start condition to SLAVE.
> 4. MASTER sends I2C address (7 bits + 1 RW bit) to PIC1.
>
> Here's the problem: PIC1 can't ACKNOWLEDGE the address from MASTER
> because it doesn't know if it is a valid SLAVE address. At first I
> thought that clock stretching would take care of it, but the I2C spec
> implies that clock stretching can only take place after an
> ACKNOWLEDGE (between bytes).
>
> Am I reading the I2C spec correctly, or is clock stretching allowed
> any time during an I2C transfer?
>
>
>
> Steve Rapinchuk
>
>
>
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