Jinx wrote:
>> The re-sync happens on the start bit of every byte.
>> 1.7% isn't enough to cause a problem.
>>     
>
> Are there not some protocols/methods that may not explicitly
> re-synch or am I thinking of something else ?
>
>   
Some hardware UARTS make 16 samples per start bit, some 64 samples, a 
few only
4 to 8 samples.  As long as the error  does not fall out of a  bit by 
the end of a frame,
there are no errors. The higher the sampling rate, the more reliable the 
UART.

The hardware UART locates the start bit after sampling several times, 
and then resynchs
its sample point in a way that subsequent bits are sampled IN THE MIDDLE 
of the remaining
8 data bits. Since the UART won't resync until the NEXT start bit, if 
the error is not great, no
data is lost. At the very first data bit, the sample is made in the 
CENTER of the bit, the next
data bit will sample at the center PLUS (or MINUS) the error percentage. 
The next data bit
will sample at the center PLUS (or minus) the 2x(error %), the next one 
3x(error %), etc. For
a typical 10-bit frame (start bit + 8 data bits + stop bit) an error of 
1.7% makes the last bit
sampled at the center +/- 17%, which is acceptable assuming that the 
UART properly locates
the CENTER in the first place.

The problem is that if the error rate is higher than 5-6%, unless extra 
stop bits (or dead spaces)
are forced into the data transfer, the start bit will have trouble 
resyncing reliably. This might be
what you are thinking about. Whenever I use a PIC with internal RC, I 
manually add extra
dead space equal to two stop bits minimum after each byte.

Software UARTS are usually unable to precisely locate the center, thus 
adding another source
of error to the protocol, usually another percent. There are so many 
ways to write a software
UART that the error rate is not easily predictable. One advantage that 
software uarts have is that
they can choose to ignore stop bit errors, or even resync slightly on 
each bit, so a small gain can
be achieved and compensate for the imprecise action of the start bit 
timing.

--Bob
 
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