> situation is lot more complicated

More like a completely different problem

> 0-2,4v  output 0-1023 with 2's complement format and enable a bit
> 2.6-5.0v  output 0-1023 disable the bit. While it is in between 2,5v 
> should output 0
> 
> any idea?

2 x 16F88 **. One with a Vref+ =2.4V, Vref- = 0V, the other
with Vref = Vcc, Vref- = 2.5V. A combination of an ADC and
window comparator -> a high-resolution ADC either side of a
deadband

** any PICs with Vref-

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