Wortinguk wrote...

>I'm building a recording temperature probe, using a LM335, 16F627 (intRC
>4MHz osc) and LCD.
>
>I have set up as per the Microchip AN700 Delta-Sigma 10 bit ADC and its code
>sample. I have a 10k pot driving Vin to a T network of 47k resistors and 100nF 
>on the ground leg.  The capacitor is on RA0/AN0, the feedback is RA3 and 
>external 2.5v ref (5v divided by two 10k) on RA2/AN2.
>
>It looks like it works fine, swing the pot and I see conversion readings of
>0 upto 1015.  However I plotted ADC readings against Vin and there is plateau 
>at the value of 512 starting at Vin of 2.2v and ending at 2.8v.
>Above and below this mid plateau there is a linear response.
>
>I have tried code mods (like using precharge, using other ports(RA6/7) and
>comaparator) and get the same issue.
>
>Not knowing the Delta Sigma method, I'll ask here if anyone knows if this is
>normal or not?

Yes, what you are seeing is quite normal for an AN700-type design
in which the RC values have not been chosen carefully.

>Is Delta Sigma a conversion of 2 halves?

No, it isn't.

People who use the AN-700 "delta-sigma" design need to be aware
that there is an optimum value for the RC time constant of the T
network: make the capacitor or the resistors too big, and the
circuit responds sluggishly and becomes very sensitive to
comparator threshold noise; make them too small, and the transfer
function (i.e., the plot of output count vs. input voltage)
assumes a shape commonly known as the "Devil's Staircase", with a
large "flat spot" at the 50% point and smaller flat spots at 25%
and 75%, and still smaller flat spots at other integer-ratio
points where the integers are larger.

I haven't seen any discussion of these effects in any of the
application notes or other material describing these "El Cheapo
ADC" designs, but they have been documented elsewhere, most
notably in Orla Feely's paper, "Nonlinear Dynamics of
Discrete-Time Electronic Systems" (IEEE Circuits and Systems
Journal, Vol. 11, No. 1, March 2000) as well as other works by
her on the effects of integrator leakage in delta-sigma ADCs.

The bottom line of all this is: make your capacitor or your
resistors bigger.  From the size of the "flat spot" you describe
(from Vin of 2.2v to 2.8v), I would say make the capacitor a LOT
bigger; in fact, you might want to check to make sure you
actually used a 100nf capacitor, and not a 100pf capacitor, as
that is a VERY large flat spot you're experiencing.

Hope this helps a bit...

Dave D.
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