It's not MEANT to be a conversion of two halves BUT (bitter) experience shows that you can get unexpected steps along the way. Can be a single one at half point as you are seeing or others at 1/4, 1/8 etc points. You can simulate the SD action using either a conventional programming language or even, quite easily a spreadsheet. You can get the step action on the simulator, showing it's not a 2nd (3rd?) order effect. Some people seem to do it without problems. Others (me included) have had endless grief with the method for reasons which are not always obvious. Sadly. You need to make sure that none of your assumptions are too far from ideal. Is the time constant of the filter sensible wrt to the signal and switching frequencies, is the input impedance in significant compared to the input resistor, is the comparator symmetric (enough), is the comparator ideal enough (offset, slew rate, hysteresis, ...). Scott Datallo has reported excellent results using a PIC digital input pin as the comparator. I had endless strife and low accuracy using a "real" comparator inside a Z8+ processor. That's what you get for using Zilog products. (YMMV with Zilog but mine certainly never will ever again).(Not because of the Sigma Delta experience but because of the 'support' [or not] that they provided in time of deepest need). Do note, and I haven't checked your code, that Sigma Delta DEMANDS an isochronous comparator loop. The time to pass through the loop once MUST be constant for all 4 possible input/output conditions and regardless of ANYTHING that happens along the way for any reason. It's far easier to get this wrong than to get it right. PIC makes it easy enough to get it right. Some processors with variable branch execution times make it very hard. Beware that extra delays due to eg interrupt service routines do not eat your lunch. Russell:: ----- Original Message ----- From: "Vasile Surducan" To: "Microcontroller discussion list - Public." Sent: Thursday, December 28, 2006 9:39 PM Subject: Re: [PIC] Delta Sigma ADC - a conversion of 2 halves? > You've spent too many HW resources for a 10bit AD. Use a PIC with a > built in AD converter. As long you have a 2.5v reference, a low > performance comparator (including offset and comutation jitter) may > gave you such a big offset of +/-0.4V. But it's still too big... > > Vasile > > On 12/27/06, Wortinguk wrote: >> Hi. >> I'm building a recording temperature probe, using a LM335, 16F627 >> (intRC >> 4MHz osc) and LCD. >> >> I have set up as per the Microchip AN700 Delta-Sigma 10 bit ADC and >> its code >> sample. >> I have a 10k pot driving Vin to a T network of 47k resistors and >> 100nF on >> the ground leg. >> The capacitor is on RA0/AN0, the feedback is RA3 and external 2.5v >> ref (5v >> divided by two 10k) on RA2/AN2. >> >> It looks like it works fine, swing the pot and I see conversion >> readings of >> 0 upto 1015. >> However I plotted ADC readings against Vin and there is plateau at >> the value >> of 512 starting at Vin of 2.2v and ending at 2.8v. >> Above and below this mid plateau there is a linear response. >> I have tried code mods (like using precharge, using other >> ports(RA6/7) and >> comaparator) and get the same issue. >> >> Not knowing the Delta Sigma method, I'll ask here if anyone knows >> if this is >> normal or not? >> Is Delta Sigma a conversion of 2 halves? >> >> >> movlw 0x06 ; Comparator module - 2x >> common ref with outputs >> movwf CMCON ; RA0, 1 & RA2 are analog >> inputs, RA3 & 4 are output >> >> SelBank TRISA ; >> movlw B'00000111' ; RA4, 6 & 7 are outputs - >> not connected >> ; RA5 is MCLR - dont care >> ; RA3 is DeltaSigma ADC >> output >> ; RA0, 1 & 2 are analog >> inputs, see CMCON above >> >> >> movlw 0x03 ; Comparator module - 2x >> common ref no output >> movwf CMCON ; PORTA.2 is AN2 and is ext >> VREF ~2.5v >> ; PORTA.0 is AN0 and is >> 100nF cap input >> ; PORTA.DSADC_Obit is output >> bit >> loop >> btfsc CMCON, C1OUT ; Is comparator high or low? >> goto complow ; Go the low route >> comphigh >> nop ; necessary to keep timing >> even >> bcf PORTA, DSADC_Obit ; PORTA DSADC_Obit = 0 >> incfsz NumL, f ; bump number lo byte >> goto eat2cycles ; >> incf NumH, f ; >> goto endloop ; >> ; >> complow >> bsf PORTA, DSADC_Obit ; Comparator is low >> nop ; necessary to keep timing >> even >> goto eat2cycles ; same here >> eat2cycles >> goto endloop ; eat 2 more cycles >> endloop >> incfsz counter,f ; Count this lap through the >> loop. >> goto eat5cycles ; >> incf counter+1,f ; >> movf counter+1,w ; >> andlw 0x04 ; Are we done? (We're done >> when bit2 of >> btfsc STATUS,Z ; the high order byte overflows to >> 1). >> goto loop ; >> goto exitADC ; >> eat5cycles >> goto $+1 ; more wasted time to keep >> the loops even >> nop ; >> goto loop ; >> exitADC >> movlw 0x06 ; let the comparator output >> preset the input >> movwf CMCON ; >> >> >> >> -- >> http://www.piclist.com PIC/SX FAQ & list archive >> View/change your membership options at >> http://mailman.mit.edu/mailman/listinfo/piclist >> > -- > http://www.piclist.com PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist > -- http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist