Hi, 

> > I was trying to use the pin RA4 in 16F877A as input or 
> output but it 
> > seem to not respond as the rest of the pins...is there any 
> setting i 
> > should consider other than TRISA and ADCON1
> 
> RA4 on most (all ?) PICs, is an open-drain output and ST 
> input, so if you haven't got a pull up resistor it won't 
> behave as you might expect it to

That solves the issue when RA4 is used as an output.

But I have also an issue with RA4 as an input.
The signal source to this pin is a TTL-Level signal.

I am using PIC16F872.

I have the strange idea, that if I am using a certain combination of
analog inputs on RA, RA4 is not working properly anymore.

Here are some parts of my code:


INIT (not complete)


		movlw	B'00000000'	; PORTA values
		movwf	PORTA




		movlw	B'00111111'	; PORTA directions
		movwf	TRISA		; RA5	(A. In)              
		                  ; RA4	(D. In)      
		                  ; RA3	(A. In)
		                  ; RA2	(A. In)              
		                  ; RA1	(A. In)             
		                  ; RA0	(A. In) 




		movlw	B'00001010'	; AD converter configuration
		movwf	ADCON1		; bit<7> 0:left justified
					; bit<6,5,4> no function
					; bit<3,2,1,0> 4 analog input, 1
reference
					
		movlw	B'00000111'	; OPTION_REG register setup
		movwf	OPTION_REG	; bit<7> PORTB pullup: enabled
					; bit<6> INTEDG interrupt edge
select: falling
					; bit<5> TMR0 clock source:
internal
					; bit<4> T0SE Timer0 source edge
select: low to high
					; bit<3> PSA prescaler
assignment to Timer 0
					; bit<2,1,0> prescaler 1:256
(102,4 us)    


MAIN Loop(not complete)


		btfsc	PORTA,RA4	; check the signal, is it zero?
		goto	VIDOK		; not zero, the video signal is
valid


And here I have the problem. It seems, that PORTA,RA4 is always reed as
0, equal if the TTL level at the input is 1 or 0.


Regarding the manual of the 16F872 I found the table for the A/D
configuration which is also al little bit strange.


REGISTER 10-2: ADCON1 REGISTER (ADDRESS: 9Fh)

bit 7 bit 0

bit 7 ADFM: A/D Result Format Select bit
1 = Right justified. Six Most Significant bits of ADRESH are read as
'0'.
0 = Left justified. Six Least Significant bits of ADRESL are read as
'0'.

bit 6-4 Unimplemented: Read as '0'

bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits:

0000 	A 	A 	A 	A 	A 	VDD 	VSS 	8/0
0001 	A 	VREF+ A 	A 	A 	RA3 	VSS 	7/1
0010 	A 	A 	A 	A 	A 	VDD 	VSS 	5/0
0011 	A 	VREF+ A 	A 	A 	RA3 	VSS 	4/1
0100 	D 	A 	D 	A 	A 	VDD 	VSS 	3/0
0101 	D 	VREF+ D 	A 	A 	RA3 	VSS 	2/1
011x 	D 	D 	D 	D 	D 	VDD 	VSS 	0/0
1000 	A 	VREF+ VREF- A 	A 	RA3 	RA2 	6/2
1001 	A 	A 	A 	A 	A 	VDD 	VSS 	6/0
1010 	A 	VREF+ A 	A 	A 	RA3 	VSS 	5/1
1011 	A 	VREF+ VREF- A 	A 	RA3 	RA2 	4/2
1100 	A 	VREF+ VREF- A 	A 	RA3 	RA2 	3/2
1101 	D 	VREF+ VREF- A 	A 	RA3 	RA2 	2/2
1110 	D 	D 	D 	D 	A 	VDD 	VSS 	1/0
1111 	D 	VREF+ VREF- D 	A 	RA3 	RA2 	1/2


In the last column, the number of AD channels and the number of
Ref-Channels is given.
But some of the configurations are shwoing a higher number as AD
channels are available.
I am using 1010, which means 4 AD and one Ref, but the table is showing
5/1.
Is there a bug in the 16F872, that RA4 is not usable in those
configurations? Or only a copy and paste issue in the manual.




THX

Jens

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