18F8310, running in MC mode. Data sheet says in all modes, has complete access to data ram area tho.... peter green wrote: > -----Original Message----- > From: piclist-bounces@mit.edu [mailto:piclist-bounces@mit.edu]On Behalf > Of alan smith > Sent: 08 December 2006 21:48 > To: Microcontroller discussion list - Public. > Subject: RE: [PIC] movwf vs movff > > > OK...forgot about the access bit, but it should have worked since > the reg value is located at 0x46 register space. Now, if I set > the access bit to 1, it works. But....if I move the register to > the beginning of the space..ie....0x20, it works with no access > bit set. It caught me off guard since it had been working but > then I added in some additional registers inbetween so it pushed > it further down the register space. So if ignoring BSR allows > you to register the first 128 bytes....and I had it located at > 0x46 (dec 71) then it should have worked in anycase? i thought so too, which pic are you targetting (i'm assuming its an 18 series because you mention movff)? i belive the access bank arrangements may vary a bit. also you aren't running the processor in extended mode are you (if its a second gen 18 series) -- http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist --------------------------------- Want to start your own business? Learn how on Yahoo! Small Business. -- http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist