In SX Microcontrollers, SX/B Compiler and SX-Key Tool, bean wrote:

pjv,
  Currently the delays in SX/B are just calculated from the clock speed.
  How does the delay look "give up" it's time slice when in a loop ?
  So if you have a "PAUSE 1" and the thread is given a time slice every 10uSec, then does it just "give up" it's slice 100 times ?
  Of course the compiler would need to "know" at compile time that the thread has a 10uSec time slice.
  How do you handle the __PARAMx variables in global RAM ? Do they need to be swapped for every task at every time slice ?
  Can you show some pseduo code of how you think it should be done ?

Bean.

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