Thanks again Vasile,

I have requested the datasheet already, bust since you have to sign 
and NDA (just a bunch of idiots working at their marketing dept.), 
this take time for the paper work to take place and I needed the 
datasheet asap.
The clock is 14.31MHz, but a phase difference should not count for as 
long as it does not add to more than a half line period or so (the 
switching occurs during the equalizing pulses on the VBI). I think 
the receiver should adjust to this small phase difference between 
frames. In the end a single TBC on the matrix output should fix this 
with no problem. I have done an experiment with one frame 
synchronizer at the output and it compensates for about 10% frame phase error.

Thanks again,
Mircea Chirciuc

At 02:00 PM 11/5/2006, you wrote:
>request a datasheet:
>http://www.via.com.tw/en/support/search/IGResult.jsp?query=VT1622&search.x=46&search.y=8
>
>Any long route will create clock skew. So, if you have clock route of
>about 20cm lenght or so, it's very possible to have different clock
>phase between the source and the load. So everything depends of clock
>frequency and how good is adapted
>om every chip input.

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