In SX Microcontrollers, SX/B Compiler and SX-Key Tool, George Herzog wrote:

I came across some code that needs tight delays and doesn't use NOP.
Instead, it uses JMP + 1.

 

Appaently this is for 2 clock cycles rather than one.

 

There is also mention of a 4 clock cycle delay in a PIC book I have, but nothing in the Parallax texts about these handy building blocks.  I suppose I can use them without figuring them out, but I am a bit concerned if they are completely compatible because the SXes use the pipeline in a tighter fashion.

 

You can even have 4 inside 4 for 16 clock delays.

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