On Mon, 2006-10-23 at 22:10 +0300, Vasile Surducan wrote: > On 10/23/06, alan smith wrote: > > Personal experiance....bring every unused signal out. If you can do via in pad, then it makes it easier since they will all be on the underneath. Is this an ASIC or an FPGA? > > It's and FPGA which will become an ASIC. > However, what if your PCB space will be some 52x100mm and you'll have > another 500 *balls* device and some 90ball memory, and..., and.... > Where the hell you're bring every unused signal out ? Well, it depends on what you want to do. Me, in that situation would build a prototype set of boards bigger then the size you mention bringing every unused pin to an accessible point. I'd then refine the design, ensure everything works, and build a second board at the size required with only a few unused pins accessible. That's just me. It's a matter of risk. If you feel you know the future requirements of the board well enough to limit yourself to the pins you use go ahead. Generally, I play it safe as much as possible. There's nothing worse then having to spin a board simply because you could have brought one used pin to a pad. I work in a mostly prototype environment, and we even bring supposedly "NC" pins out to pads, it's saved us in the past. TTYL -- http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist