On 10/23/06, alan smith <micro_eng2@yahoo.com> wrote:
> Personal experiance....bring every unused signal out.  If you can do via in pad, then it makes it easier since they will all be on the underneath.  Is this an ASIC or an FPGA?

It's and FPGA which will become an ASIC.
However, what if your PCB space will be some 52x100mm and you'll have
another 500 *balls* device and some  90ball memory, and..., and....
Where the hell you're bring every unused signal out ?


>
>
> Vasile Surducan <piclist9@gmail.com> wrote:
>  Hi,
> I have a quite large BGA package to route (484 pins).
> The question is (only for those who already did such PCB designs),
> which would be the best way to manage the unused pins: deleting the
> pads or keep them on the PCB ? I presume will be less than 10 layers,
> but the overal thickness must be quite low (around 0.5-1mm)
>
> thx,
> Vasile
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