Andy Tuthill wrote:
> Hi Bob,
>
> I had a project recently with a 12F675 that I wanted to do 3 sequential 
> eeprom writes for settings data.  The plan was to let the eeprom interrupt 
> send the next data byte because the write should be complete at that time.  
> What I found was that if I started another write cycle as soon as the WR bit 
> reset that I had problems and usually nothing ended up in eeprom.  As I 
> understand the data sheet the eeprom interrupt happens at the end of the 
> cycle so I should be free to start another write.  This works fine in other 
> chips.
>
> In the end the work around I found was to rearrange the code to give the 
> chip loads of time before trying to write the next byte.  I never tried to 
> find out just what time threshold was required but I gave it massively 
> longer than the 5 ms I normally associate with a write cycle.
>
> This may or may not be another aspect of what you are describing.  This does 
> tend to differ from the sleep option to a degree because I don't watch the 
> WR bit now while the sleep does.
>
>   
Yes. Maybe what is happening is simply that using the WR bit simply 
doesn't work, whereas the EEIF bit
does.

Yours is another possibility. Actually I thought of trying that, but I 
knew that the flash time would be greatly
extended at 3V, so would cause a LOT of extra delay (I have to write 6 
bytes). I ran some tests on another
PIC a while back at 3V and got o'scope readings of over 6mS, and 5V PICs 
would flash in 3.5mS or so.

What is annoying me most is that these nanowatt EEPROM problems are 
incredibly time consuming, and they
make me look like an idiot. These puppies also drop bits, so have to be 
refreshed periodically. The PIC16C
devices didn't have the convenience of flash, but they certainly had a 
solid, usable EEPROM array.

--Bob




> Regards,
> Andy
>
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