In my interpretation it means that there is a problem with the WR that it
will be zeroed out internally before the actual write had been done. So when
the CPU put into sleep mode it does not occur. So as far as I concern the
sleep is just a workaround but I may completly wrong?

Tamas


On 19/10/06, Michael Rigby-Jones <Michael.Rigby-Jones@bookham.com> wrote:
>
>
>
> >-----Original Message-----
> >From: piclist-bounces@mit.edu [mailto:piclist-bounces@mit.edu]
> >Sent: 19 October 2006 19:01
> >To: Microcontroller discussion list - Public.
> >Subject: [PIC] Notice: PIC12F629 has same EEPROM errors as
> >PIC`16F628 et al
> >
> >
> >Thanks again, Alan Pierce!
> >
> >I have been experienced incredible EEPROM unreliability with
> >the 12F629. I have spent days on it. It appears that chip
> >revision 0xC of the PIC12F629 (12F675 I will test later) has
> >the SAME problem as the PIC16F627, PIC16F628, and PIC16F648,
> >in that the CPU operation is NOT suspended while the WR bit of
> >EECON1 is true.
>
> Bob,
>
> Sorry if I haven't quite grasped this, but are you saying that some PICs
> do suspend the CPU during writes to the EEPROM?  I know the CPU is suspended
> when writing to Flash (on those PIC's that support self writes), but I have
> never encountered one that suspends when writing to EEPROM.  This behaviour
> would somewhat negate the advantage of using the EEIF interrupt wouldn't it?
>
> Regards
>
> Mike
>
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