> > Input leakage current (pin at high impedance) is +/- 1uA when
> > Vss =3D< Vpin =3D< Vdd
>
> =B1 1uA times 14 is =B1 14uA...
>
> Could it be that making them outputs results in less current?
>
> Gerhard

My bad, I had to rush off to rescue a glue joint and sent the
mail without finishing it

I was going to add that I have a 12F675 running on 2 x AA
(3.3V) with a mix of inputs and outputs

GPIO0 (output) - normally '0'
GPIO1 (output) - normally '0'
GPIO2 (input) - 390k pulldown to 0V
GPIO3 (input) - 100k pullup to Vbatt (Mclr)
GPIO4 (output) - normally '0'
GPIO5 (output) - normally '0'

It uses less than 15nA when SLEEPing, so although the d/s
says "1uA", the true figure is or could be way less than that

You might expect 1000nA from the 100k pullup alone, as
it's capable of passing 33000nA

-- =

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