Brent Brown wrote:
>>> In line with that: I found out that running your system with TWO
>>> stop bits (rather than one) allows the UARTS at each end to resynch
>>> between characters. This usually allows the system to work fine with
>>> a 3-4% error.
>>>
>>> --Bob
>>>       
>> Thanks Bob,
>>
>> That's an excellent idea. The next question is how does one program
>> the PIC UART to send two stop bits - do you have to set it in 9 bit
>> mode and make the 9th bit the extra stop bit?
>>     
>
> To ansmwer my own question I enabled 9 bit transmission (TX9 = 1) and set the 9th 
> data bit (TX9D = 1), which makes it look like 8 bit data with two stop bits.
>
> I tested this by making the transmittting PIC send 2 stop bits, as above, and left the 
> receiving PIC configured as previous (8 bits of data 1 stop), and changed the clock 
> frequency to determine the point of comms failure.
>
> Firts I increased the clock frequency of the receiving PIC, by increasing OSCTUNE 
> value, until comms failed. It fails at about the same point, regardless of sending 1 or 
> 2 stop bits - when RxD was about 3% faster than TxD.
>
> Next I reduced the clock frequency of the receiving PIC until comms failed. Same 
> results as above - more or less no difference in the point at which comms failed 
> regardless of sending 1 or 2 stop bits - when RxD was about 3.5% slower than TxD.
>
> Well, it seemed like a good idea and was worth trying, but I can't explain why it 
> didn't work as hoped.
>
>   
Let's analyse it, your results might be valid:

Your transmitter sends a character that is 3% too FAST. The receiving 
UART picks a sampling point in the middle
of the start bit where it EXPECTS the middle to be.  That makes the 
receiving UART sample at a point 3%  PAST
the center for each bit, each bit accumulating a 3% error. The first 
stop bit will be off  3+3+3+3+3+3+3+3+3+3 (start bit
plus 8 bits plus 1st stop bit) so the first stop bit will be sampled at 
a point 30% PAST the center (80%); worrisome, but
NOT a big deal. At 5% error, the 1st stop bit will be sampled at a point 
50% PAST the center, a disaster, since 50% past
the center might pickup the NEXT character's start bit if only one stop 
bit is used. But if TWO stop bits are used, 5% is a
reasonable number.

At the same time, YOUR recever's clock is 3% faster than the character 
coming in, so when the client sends a start bit for
a 10-bit character (1 stop bit), it starts off 3% early and accumulates 
until the first stop bit is sampled, at a point 30% PRIOR
TO the center. Again 3% error is not  a major problem, but 5% IS, 
because  the 1st stop bit might be sampling the last data
bit.  But sending two stop bits does NOT help here.

Looks like the two stop bits helps only in one direction, NOT in the other.

Can you get by with 7bits, two stop bits? You should get 4%  operation 
both ways.

BTW, Why are you trying to operate past 3%? Microchip has never rated 
its chips' RC clock to be better than 3%...

--Bob
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