On Mon, 18 Sep 2006, Phillip wrote:

> It would check to see who the interruptee was (by looking at the PIRx flag
> bits) and then I would make yet another call the appropriate handler.
> This is the way I do my low level interrupts.

That's fine.

> When I'm in a level interrupt it can be interrupted by another low or a high
> .....me thinks.

A high or low level interrupt will not interrupt itself unless you're
doing something unusual (e.g., setting GIE in a high interrupt).

> Are high interrupt ISRs not reentrant?

They're not unless you've taken special measures to make them so.  The
fast register stack used by high interrupts is only one deep.  You'd
need to tell your compiler that your high interrupt was a low
interrupt to get full context save/restore, while still placing it at
the high vector.

>
>
>
>
>
> Phillip
> Things should be as simple as possible but no simpler
>
>
>
> Phillip Coiner
> CTO, GPS Source, Inc.
>
>
> Your source for quality GNSS Networking Solutions and Design Services, Now!
>
> -----Original Message-----
> From: piclist-bounces@mit.edu [mailto:piclist-bounces@mit.edu] On Behalf Of
> John Temples
> Sent: Monday, September 18, 2006 7:53 PM
> To: Microcontroller discussion list - Public.
> Subject: Re: FW: [PIC] Trouble getting my ISR high
>
> On Mon, 18 Sep 2006, Phillip wrote:
>
>> The data sheet does not say you can't have more than one high priority
> ISR.
>
> It does say that there is one high priority interrupt vector.  How are
> you going to place two ISRs in the same place?
>
> --
> John W. Temples, III
> -- 
> http://www.piclist.com PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>
> -- 
> http://www.piclist.com PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>

--
John W. Temples, III
-- 
http://www.piclist.com PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist