Vasile Surducan wrote:
> That's an interesting design. I didn't look to the MAX9201 datasheet,
> but if I add 7nS for the rising edge and another 7nS for the falling
> edge, plus at leat 1nS for high level setling time, it means 15nS or
> an input bandwith of about 66MHz. The logic analyzer will probably
> have false trigger around 50MHz, I don't know for sure.

Actually, it's 7ns propagation delay, with a rise time of 2ns and a fall time 
of 1ns.

> Do you mean "analog input" as a DSO input ?

Yup. Eight digital logic inputs and a single analog (DSO) channel.

> Usualy there is nothing at the probe tip except the clip. At the
> analyzer input could be a terminator (like the one from California...)
> but that depends on the probe's wire lenght and arrangement. I'll
> think to a resonable input impedance for the beginning, covering most
> of the logic families.

The problem is, there's no real data on the design of the 
isolation/compensation circuits. For instance, one of the old HP analysers 
(the 1651B) used this arrangement:

                    +-[ C=8.2pf ]-+
                    |             |
In >---[ R=249R ]--*-[ R=90k9  ]-*---> Out to analyser

(the manual says the total load on the target device is around 100k)

What I want to find is some information on what this type of circuit does, and 
  how to pick component values for it. I know there probably needs to be 
another resistor from "Out to analyser" to GND, and I guess that needs to be 
around 8-9k. What I don't know is if my guess is accurate and if not, how to 
go about design something else to work with my input amplifier.

Thanks.
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