On 9/8/06, Philip Pemberton <piclist@philpem.me.uk> wrote:
> Hi,
>   A few of you might remember me mentioning my current pet project - a
> PIC-based handheld logic analyser / oscilloscope. I've got most of the core
> design done (to the point where I can 'program' a simulated model of the CPLD
> and have it run normally), but I'm having a few problems with the design of
> the input circuitry.
>
>   At the moment, the logic input circuitry consists of a pair of Maxim
> MAX9201 quad 7ns comparators, a 5:1 potential divider. That means that given a
> 10V input, the comparator will see around 2V. A digital-to-analogue converter
> provides a 0-2V reference voltage, which is shifted and then doubled to
> produce an adjustment range of -2 to +2V. This allows the input comparator to
> switch at any voltage from -10V to +10V, which covers the threshold ranges
> required for ECL, TTL and CMOS (and probably other logic families as well).

That's an interesting design. I didn't look to the MAX9201 datasheet,
but if I add 7nS for the rising edge and another 7nS for the falling
edge, plus at leat 1nS for high level setling time, it means 15nS or
an input bandwith of about 66MHz. The logic analyzer will probably
have false trigger around 50MHz, I don't know for sure.



>
>   At this point it's probably worth pointing out that the sampling circuitry
> has a maximum clock rate of 100MHz. That means the maximum square-wave signal
> frequency I'd be looking to capture would be around 50MHz. Ideally I'd like to
> load the DUT as little as possible, so I'm aiming for an input impedance of
> around one megohm.

You have to load the DUT with the impedance specified in the datasheet
for the logic family under test. Many devices at this speed required
much smaller load.


I don't mind going lower if necessary though. I'm not
> trying to build the next TDS220, I just want something small to debug
> small-ish devices. If you've ever seen a HP LogicDart, that's the kind of
> thing I'm thinking about, but with an analogue input and a few more input
> channels.

Do you mean "analog input" as a DSO input ?


>   What I'm looking for is some information on logic signal probing (or even
> something that covers basic probe design). I know I'm going to need to
> terminate the input, probably at the probe tip and at the analyser input.

Usualy there is nothing at the probe tip except the clip. At the
analyzer input could be a terminator (like the one from California...)
but that depends on the probe's wire lenght and arrangement. I'll
think to a resonable input impedance for the beginning, covering most
of the logic families.

greetings,
Vasile
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