In SX Microcontrollers, SX/B Compiler and SX-Key Tool, transistortoaster wrote:

Thanks for your response.

Frank said...
>>5. In the video display code, I understand that I must add nops to get the correct 0.3us per pixel. So 
>>I guess there's  no real question here. I did a few tricks to get 1 pixel per clock cycle at 4MHz and 2 pixels 
>>inter-tile spacing so far.

>I'd love to see how you did that ! Can you post your code ?

Sure I'll do that when I finalize. The goal of going 4MHz was to not use an external oscillator  The main issue that I overcame was to do a little shaving to not exceed the available clock cycles in the 63us ISR period. I summarize what I did :

The main idea is to prepare the pixels to be displayed from tile lookup during the Hsync and black portion of the 63us line. All the prep work is stored in a brand new 16*8 bit array. At the active video part of the 63us line, I just copy one byte at a time from the prep array and do 7 rotates to shift out the bit pattern. Your code works on 0.3us (6cc) per pixel. At 4Mhz, one cc is 0.25us, so each rotate takes 1cc  equivalent to one pixel.
 
Frank

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