In SX Microcontrollers, SX/B Compiler and SX-Key Tool, metron9 wrote:

I just ordered the SX dev kit , I have been working with the atmel chips. I am looking at cycle times listed in the documents. After trying the simulator I have a question about cycle times.

The Document SXkeyMAN2 has the following:

When the pipeline is cleared, the fetch
and decode stages are replaced with 'nop' instructions. This effectively nullifies the invalid instructions
and increases the cycle-time for that command by 3 cycles.

the following code segment
[code]
Delay		clr	Count1  		;Initialize Count1, Count2									
		inc 	count1
Loop		dec	Count1		;Decrement until all are zero	
	        jnz     loop
[/code]

First I am trying to understand the cycle time listed as 1(4) to mean 1 or 4 depending on previous code.  when would the cycle time be 4

When I simulate the code I see one cycle for 1 to 0 from 0 to 255 or any other number

The JNZ instruction changes the PC counter and adds NOP's to the pipeline but I only see 3 cycles for the JNZ instruction and one cycle for the DEC instruction. 

I ask this because after reading the documents on the pipeline and looking at the cycle times I am wondering if 50Mhz is going to be any faster for typical code than the atmel 20Mhz chip with typical instructions of 1 cycle time.

The Simulator: Is there a simulator/debugger that stepps through code so you can see the code in context instead of just the instruction that will be executed next. Seems it would be hard to follow the code as you would have to look at a listing back and forth. The code above in the simulator shows a SZ instruction. I guess after looking a bit if your code jumps within a segment it compiles to one instruction vs another instruction.

This should be interesting as it seems to have a steeper learning curve than I originally thought it would have.

Looking forward to programming the SX chips.

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