I have an application that has to capture the time of an event with 
the greatest precision possible, so the capture feature is being 
used. The 16 bit resolution was not enough, so the Timer 1 overflow 
interrupt is used to increment a counter and provide an additional 8 
bits of resolution.

First problem: TMR1 overflow ISR is called twice for each overflow. 
Simply clearing TMR1IF does not work. A search of the PIC list 
archive found a suggestion to disable the overflow interrupt 
(TMR1IE), clear the interrupt flag, and then enable the interrupt. 
This works, but is ugly. I can not find any documentation of this 
behavior in the 16F628 or mid range manuals.

Working code:
	bsf			STATUS,RP0
	bcf			PIE1^BANK1,TMR1IE
	bcf			STATUS,RP0
	bcf			PIR1,TMR1IF
	bsf			STATUS,RP0
	bsf			PIE1^BANK1,TMR1IE
	bcf			STATUS,RP0
	incf		t1_overflow,F

Questions: Is this documented anywhere? Is there a better (more 
efficient) way to do this? Do other 16F series PICs behave the same way?

Second problem: There is no interrupt priority, so the overflow count 
may be out of synch with the capture. The only solution I could think 
of is to check if the capture MSB is zero and TMR1IF is set. If these 
conditions are met, the timer has overflowed before the capture event 
but the overflow ISR has yet executed, so the overflow count is 
behind and must be incremented. Testing has been perfect - no failures.

Working code:
	incf		t1_overflow,W
	movwf		cap_ovr_save
	movf		CCPR1H,W
	movwf		cap_msb_save
	btfsc		STATUS,Z
	btfss		PIR1,TMR1IF
	decf		cap_ovr_save,F
	movf		CCPR1L,W
	movwf		cap_lsb_save

Questions: Is this sound logic? Is there a case where this will fail? 
Is there a better method or more efficient code?

Thanks,
Kevin Timmerman

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