Hello Everyone,

     I'm back again.  Putting the Stop Start Stop sequence in my
initialization seems to have fixed the inconsistent start up problem but
something new has cropped up.

     By the way, sorry for putting you all through this.  In my small
company there was a firmware engineer and an electrical engineer.  The EE
who I would normally work with to resolve this kind of thing has moved to
(presumably) greener pastures leaving me in a little deep.

      The new problem I'm seeing is that the signal looks just great when my
I2C part is not on the bus (a slave-only AD5602 DAC).  When the device is on
the bus, during the address byte SDA looks proper and acknowledges that it
received the proper address.  However, the 9th clock bit is only about half
the voltage it should be and a giant impulse follows right on its heels.
Both SCL and SDA ring, then SCL starts the next byte at the proper place but
only emits one clock before just staying low.  SDA is just sitting high at
this time.      This is in a loop and should be sending 3 bytes (one
packet), delay, and then the next packet continuously.  When this goes wrong
it only sends the first packet, what I described happens, and then it does
nothing else.

     I say this because if I send the wrong address then I get Nack'd as I
should and everything continues to look good and the infinite loop of 3 byte
packets with a delay continues on.  This makes me think that there is some
contention that is going on when the slave receives its address, although
SCL should be input only on the slave.

     Also, if I put a 500 ohm series resistance between the DAC and SCL I
still have a crappy looking signal, but it doesn't hang after the first byte
and the DAC reads even that ugly signal just fine.

     Sorry for the narrative, any input is appreciated.

Thanks,

Mart
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