On 17/07/06, Wouter van Ooijen wrote: > > > Plenty more chances to make it fail. Just a few: > - A/D acquisition time varies, also depending on source impedance Yes, it could be the same problem as the timer one, isn't it? - self-write algorithms are vastly different I am not sure what do you mean by? - read all erata, some chips need interesting work-arounds in some > situations I think it could be done by a 'knowladge database', so that if it is known that you should do something special to read data form here or there then it could automatically rewrite / extand that piece of code. - peripheral control structure varies (distribution of bits over bytes, > semantics of bits, etc) As long as those described in the INC file I think it is not a problem as it disassembles the code completly so you will get a 'meaning' of the code. So 'btfss INTCON, T0IE' is always that and as long as INTCON and T0IE definitions exists on both chips' INC file it could be translated fine. There might be some problem if ANDLW or similar applied to test / change more than one bits at a time. > - stack depth: 2/8/32 The basic principle was to reuse a code in a higher PIC rather than in a lower, but it might be possible to check the depth of a call flow if the code is not recursive. > - interrupts: 0/1/2 > - A/D resolution: 8/10 > etc etc Yep, those are more hard to do. Maybe that's why it is not worth the effort :-) Regards, Tamas -- http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist