> My doubt about this is that the other chip may have a 
> different clock freq
> so that all time related stuff would fail. For example you 
> might have to
> change time scaler for watchdog or timer interrupt, and also 
> if the code
> based on instruction cycles (aka an iteration calculating 
> time, make delays
> etc) then you have to put nops or change values for that. And 
> that's very
> hard to tell by a stupid tool which of these values have to 
> be changed to
> what.

Plenty more chances to make it fail. Just a few:
- A/D acquisition time varies, also depending on source impedance
- self-write algorithms are vastly different
- read all erata, some chips need interesting work-arounds in some
situations
- peripheral control structure varies (distribution of bits over bytes,
semantics of bits, etc)
- stack depth: 2/8/32
- interrupts: 0/1/2
- A/D resolution: 8/10
etc etc

Wouter van Ooijen

-- -------------------------------------------
Van Ooijen Technische Informatica: www.voti.nl
consultancy, development, PICmicro products
docent Hogeschool van Utrecht: www.voti.nl/hvu
 

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