Alan, On Wed, 7 Jun 2006 08:37:25 +0100, Alan B. Pearce wrote: > > 2-The PIC24 has dismal erase/write cycle lifetime. Typically 1000 but > > could be as low as 100 cycles. > > But isn't the PIC30 dsPic a "beefed up" PIC 24 (or the 24 a cut down dsPic)? > The dsPic has a higher cycle life than that, and surely the cost of a dsPic > for prototyping is negligible. I can understand going to a 24 for cost > squeezed production, but why develop on it? It's *much* more complicated than that, I'm afraid. The seminar goes through it quite well, and from the handouts and my own notes this (subject to error, omission, misunderstanding, not being able to read my own writing :-) is my understanding of the thing: There are 4 ranges of chips, 24F, 24H, 30, 33. The 30 and 33 have the "ds" prefix in their names, and include the "DSP Engine". They *all* have : - 16-bit ALUs, and can do a 16 x 16bit signed multiply in a single instruction cycle (25ns for the 40 MIPS devices - two orders of magnitude faster than a PIC18) - multiple Working registers (rather than just the W of the PICs 10/12/16/18) - two UARTs - two SPI - two I2C - 16/32 bit timers - WDT / Power management - a JTAG interface. The 30 runs at 5V, the others at 3V3. The 24F is the "Value" range, runs at 16MIPS, has built-in Real Time Clock (RTCC) and Parallel Master Port (PMP), but no DMA. It can have up to 128k of Flash, 8k of RAM. A/D is 10 bit at 500ksps. The 24H is the "Power" range, runs at 40 MIPS, has 8-channel DMA, more memory (up to 256k Flash, 16k RAM), an Enhanced CAN interface, but no RTCC or PMP ("yet")! A/D is 10 bit at 1Msps or 12 bit at 500ksps. The 24F and 24H have two address generators, so an instruction can address two memory locations at once. The 30 and 33 have three address generators, so an instruction can address three memory locations at once. The 30 and 33 both run at 40 MIPS, have the DSP engine and two 40-bit accumulators, and ECAN. A/D has two sampling units that can operate at the same time, and as with the 24H you can choose 10 bit resolution at 1Msps or 12 bit at 500ksps. No RTCC or PMP, but different models can have a CODEC interface or Motor Control (not both). They can both have up to 256k of Flash and 30k of RAM (don't know where the other 2 went! :-) The 33 has 8-channel DMA, the 30 hasn't. Overall the 30 is more limited than the 33 (need to check the specs for details), uses more power, and seems to be the early attempt that taught them how to do it better with the later ones! (IMHO, obviously). Others who attended the same seminar may have picked up other differences, or mistakes in my understanding... So it looks like simple ideas like: "develop on a 30, go into production on a 24" or whatever, really don't work unfortunately. The matrix of mismatches between the ranges (they didn't mention the Flash cycle differences, by the way) are such that you really have to be careful that you use only features that are common between the development and final devices. This has always been the case, but it seems to be more apparent with this lot! Cheers, Howard Winter St.Albans, England -- http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist