Hello Vasile,

> This behaviour is identical with a parasitic capacitance on the bus lines.
> It could be solved (if the boards are already manufactured) by trying
> an adapting resistor network near the RTL (possible near the PIC too).
> Usually a 3k3 to 10k network conected from the bus to VCC may help,
> but if the bus is very long or the RTL is supplied wrong will not help
> to much.

     i've put 10k pullup resistors on the data lines. The risetime 
droped from 1.2us to 330ns. This was measured with a 1X/10X 100MHz scope 
probe in the 10X position. Putting it on the 1X position the risetime is 
about  1.7us. It seens the probe capacitance is the main reason for the 
high risetime.

     Anyway, the application still doesn't work.

     If you have some experience with interfacing PICs to RTLs, I'll be 
happy to send you (in private) the files from my project.

     Thank you very much,

     Brusque
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