Wouter van Ooijen wrote:
>> It turned out that 5 usec delay between Vpp and Vdd rise wasn't enough
>> and I need 30 usec to program the device reliable.
>>     
>
> That might be a spec problem, but are you sure your Vdd rises that fast?
>
> IIRC I use a few ms delay.
>   
I discovered that for some PICs the time between VPP & VDD / VDD & VPP 
needs to be held precisely
to reliably acquire Programming Mode. The PIC16LF87/88 and the PICF87/88 
have to be held tight under
certain settings, such as MCLR\ used as an input and no powerup delay.

--Bob

> Wouter van Ooijen
>
> -- -------------------------------------------
> Van Ooijen Technische Informatica: www.voti.nl
> consultancy, development, PICmicro products
> docent Hogeschool van Utrecht: www.voti.nl/hvu
>  
>
>   

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