In message <00a601c67da3$1ecd7380$0201a8c0@dad>
          olin_piclist@embedinc.com (Olin Lathrop) wrote:


> But this is exactly the sort of algorithm that will have slow transient
> response.  Current demand can change very suddenly.  Look how long it would
> take this algorithm to ramp the PWM duty cycle from one end of full scale to
> the other.  Also, you could use a comparator instead of A/D to get the
> high/low decision unless you are making the setpoint soft.  The 16F648A is
> pretty much the same chip with comparator instead of A/D.  A comparator will
> allow a simple control loop to be run more often, which can often compensate
> for it being more simple.

I guess its slow reaction time is why Atmel used that algorithm in the AVR450
reference design. Incidentally, pretty much all of the calculations in the
'450 appnote are crap. As in, the theory is sound, but whoever did the
calculations either fudged the numbers on every single one, or they did them
on an FDIV'd Pentium-66...

> > What I'm getting is a spike of about 10V,
> 
> This is when a large load is suddenly removed?

No, it's a startup spike. When the circuit first gets powered up, Vout jumps
to 10V, then settles down at 5V after a few seconds.

> loop:
>   if voltage too low
>     then do a pulse
>     endif
>   goto loop

PSM (aka PFM) in other words. The exact same algorithm seems to have been
used in Mchip AN216, and looks fairly simple to implement. Only 60% or so
efficient though (and 45% worst case efficiency - only slightly better than a
linear regulator), which is a bit of a shame.

I'll have a play with the hardware tomorrow - I'll probably nip into town and
pick up a few power FETs and some decent diodes and inductors as well. At the
moment, the closest thing I've got to a power FET is a 2N7000!

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