> > 
>   VHDL. So far I want to dwell very closely to the
> gate level. I know it is going to take much longer but
> I believe it is worth playing at this  .Anyone use
> FPGA for work?
> 
> John
> 
> 
> 
At the gate level, it gets pretty tedious in VHDL.  But also you have
certain constructs in the FPGA that are not purely gates.  For example,
in Xilinx Spartans and Vertexes you have DCMs and PLLs for clock
generation.  Those are addressed as black box components in VHDL.

You also have hardware multipliers which will be accessed by using the
"*" multiply symbol in an equation.

If you insist on gate level control you can do that relatively easily
with the schematic capture but the schematics rapidly become very
unwieldy.

One possiblity is to mix-and-match between schematics and a textual
description.  By designing and placing contraints at the gate level with
a schematic, you can call these subdesigns from a higher level of
abstraction in VHDL or Verilog.  Works the other way too, design in VHDL
and create a schematic symbol with appropriate ports and tie into a
schematic.  I've used schematics for the very top level to define
sub-blocks and then write VHDL for all layers under the top.  Works
pretty well but will not be 100% portable between vendors when you do
that.


Rob
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