>Interesting! We're currently looking at the suggested
>PLD solution. I'll keep this in mind, though!
>
>THANKS!
>
>Harold
>
>
>> Assuming the 27M words/second data has a clock associated with it, and a
>> sync signal to indicate the start of the frame you could:
>>
>> 1: Use the original 27 MHz signal to drive a divide by 4 circuit to
create
>> a
>> frequency below 10MHz.
>> 2: Use that signal as the clock signal for a PIC18 with a 4X PLL
>> -- this will leave you with four pixels per instruction time on the PIC18

Of course, if you used a dsPic instead, you can get the 27/4 multiplied up
to something near 120MHz internally, giving even more processing per pixel.
One could probably get away with 27/3 as the input to the micro. It is
possible to make a /3 with symmetrical output using JK flip-flops.

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