Howard,

On Sun, 2006-04-09 at 13:59 +0100, Howard Winter wrote:
> Don't forget that the interupt is on Port B *Change*, and it will set the Interrupt Flag whether Interrupts 
> are enabled or not.  Your ISR clears the flag at the beginning, which is often the wrong place, and certainly  
> is in this case (potentially each bit will set it again).  Even if you do clear the flag at the end, if your 
> ISR doesn't wait until the Rx line goes finally high before the RETFIE, the interrupt will trigger when it 
> does go high.

Thanks for the tip. I'll add a small loop to the end of the ISR....


> Incidentally, how does your scheme send something with the first bit = 1?  You seem to take your first sample 
> half a bit-time after the initial transition to low, so you have no "start bit", implying that you'd have a 
> short high-low-high pulse to start the byte and represent a 1 in the first bit - this is not a good idea as 
> the frequency of that pulse is way above the rest of the data, making it more easily mangled on the way, with 
> possible misreading of the first bit.

There is a very short start-bit in there, but it's only a few uS long
and doesn't show up easily on my scope. My transmit routine brings the
line low for 10uS, then starts shifting the byte out. I could write a
990uS delay for the first bit so the receiver lines up precisely in the
middle of each bit, but I figure +10uS off the middle of a 1ms bit is
allowable. Is that what you meant? Re-reading your paragraph I'm not
sure if you mean a start-bit that's of much shorter bit-time than the
rest of the data is a bad idea.....

Cheers,

Tim

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