Tim,

Don't forget that the interupt is on Port B *Change*, and it will set the Interrupt Flag whether Interrupts 
are enabled or not.  Your ISR clears the flag at the beginning, which is often the wrong place, and certainly  
is in this case (potentially each bit will set it again).  Even if you do clear the flag at the end, if your 
ISR doesn't wait until the Rx line goes finally high before the RETFIE, the interrupt will trigger when it 
does go high.

Incidentally, how does your scheme send something with the first bit = 1?  You seem to take your first sample 
half a bit-time after the initial transition to low, so you have no "start bit", implying that you'd have a 
short high-low-high pulse to start the byte and represent a 1 in the first bit - this is not a good idea as 
the frequency of that pulse is way above the rest of the data, making it more easily mangled on the way, with 
possible misreading of the first bit.

Cheers,


Howard Winter
St.Albans, England


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