Phil

I've always wanted to build a Mixed signal DSO. No chance we could add 4 =

channel analog signals. I could work in the 4 layers PCB, power supply and =

analog adquisition. Analog devices parts are going into the 1GS per second =

and more (with carefull PCB desing).

What you think.....

regards,





Ing. Sergio Alejandro Gonzalez
e-mail : sagonzal@fi.mdp.edu.ar
Facultad de Ingenier=EDa - Laboratorio de Instrumentaci=F3n y Control =

Universidad Nacional de Mar del Plata
Ave. Juan B. Justo 4302
Mar del Plata, Bs.As.
Argentina.
Zip B7608FDQ
Tel. +54(223) 481-6600 ext.254
Fax. +54(223) 481-0046 ext.254
http://www.fi.mdp.edu.ar/


At 08:04 AM 4/5/2006, you wrote:
>OK folks - quick update on the logic analyser project...
>
>   1) I've got the triggering and bus interface Vlog code done, checked and
>tested. That just leaves the clock divider and acquisition control left to
>do.
>
>   2) I can't get any 10ns RAMs, and even if I did I doubt they'd actually=
 be
>able to write at the full 100MHz without thoroughly violating the data hold
>time specs.
>
>   3) I can, however, get 15ns RAMs that would easily be able to handle a
>50MHz (or probably a bit faster) sample clock. They're Cypress CY7C1021s, =
in
>case anyone feels like pulling the datasheet and reading it. 44-pin SOJ,
>1.27mm pin pitch (no smaller than a SOIC). DigiKey have got the 10ns versi=
on,
>which should be OK as a substitute. No guarantees on sample rate, but I wa=
nt
>20MHz as a bare minimum, and I'm actually aiming for 50MHz.
>
>   4) I've got the equipment to do double-sided PCB manufacture, but I don=
't
>have anything to do plated holes with. If anyone wants to donate a few
>Multicore Copperset bail-bars and a 0.9mm pencil, I'm not going to stop th=
em
>:). I've already got a modified centre-punch, 0.85mm drill bit and a small
>anvil, so that's most of the tools covered.
>
>   5) Construction is going to be mostly SMD but with some through hole pa=
rts
>(connectors mostly). I hate drilling holes in PCBs. Offboard connections a=
re
>going to be USB, 9-12V power and 16-bit bus input. I estimate the final bo=
ard
>size to be somewhere around Eurocard size, though with a bit of luck (and a
>lot of SMDs) I might be able to get it down to half-Eurocard.
>
>   6) Schematics will be released as-and-when. I want to get the basic
>hardware design stabilised before I release anything. Thankfully the CPLD
>should allow me to fix most Silly Bugs (tm) without cutting and rerouting
>tracks.
>
>   7) I'm using a PIC18F4550, mainly because that's the only USB PIC I've =
got
>in my junk box.
>
>Thanks.
>--
>Phil.                         | Kitsune: Acorn RiscPC SA202 64M+6G ViewFin=
der
>philpem@dsl.pipex.com         | Cheetah: Athlon64 3200+ A8VDeluxeV2 512M+1=
00G
>http://www.philpem.me.uk/     | Tiger: Toshiba SatPro4600 Celeron700 256M+=
40G
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