In SX Microcontrollers, SX/B Compiler and SX-Key Tool, Peter Van der Zee wrote:

Hi Michael;

Well, we are still on opposite sides, and I will do the tests.

Sure, I acknowledge that the buffer fills up, because that was proven it a test. But the REASON it fills up is now the issue.

Yes, I fully understand that the receive UART and re-transmit UART are working form the same clock, and hence there is no "slip" between them.

In postulating all clocks were the same, that was simply a reference point for determining timings.

My point was, said in another way, is that the software UARTs I designed dealt with received data before the end of the complete character, and THAT is what provides the "extra" time to permit the receiver/retransmitter pair's clock to be a little slower than the foreign clock.

I hope to get to this in the next several days, so please stand by......

Cheers,

Peter (pjv)

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