In SX Microcontrollers, SX/B Compiler and SX-Key Tool, Peter Van der Zee wrote:

Hi All;

 

One of the posters in another thread was using dual VP UARTS at 115200 in a relay format; receiving data from one into a 32 byte buffer, and transmitting it back out from the buffer. Two UARTS were specified so bi-directional streams could be handled. The problem was, at high data rates there were some data errors occuring; probably due to inconsistent timing in the bit-banging process.

 

I re-wrote the software using a shadow register in the ISR which is used to set and read the outs and ins at consistently predictable times (deterministic), and letting the mainline deal with writing and reading the shadow at will (almost).

 

Since the code is reasonably tight for the number of cycles available in the 145 instruction (2.9 uSec 3X oversampling) ISR tick, I added a "Headroom" monitor to see how close we are getting to running out of instructions........at a continuous full tilt rate it's close.

 

For anyone who wants to try this code for their own purposes, have at it........

 

I use a state machine for each of the transmit and receive functions of each UART; thus four total.

 

Since I did not have an external source for 115200 8N1 serial data, I faked it with internally gererated stuff into the buffers, and observed the results on an oscilloscope. All appeared to be working OK, but if a gremlin is discovered, please let me know.

 

So, UART1 receives data in a continuous stream and puts it into a 32 byte circular non-overwriting buffer located at $50 through $7F. UART1's transmitter detects data content in the buffer and sends it back out, also at 115200. The transmitter's buffer pointer will not "lap" the receiver's pointer.

 

The identical happens in UART2, with it's 32 byte buffer located at $D0 through $FF.

 

If you want slower baud rates, it's best to scale the four state timers appropriately.

 

This of course is not the only, or best way to tackle this requirement. If one could choose the transit hardware pins to be at the extremes of port registers (bit 7 and bit 0), then some more effeiciency can be gained.

 

Also, the code could be tightened op considerably, but perhaps at the expense of performance.......clearly not an issue for slower data rates such as 38400.

 

Have fun and let me know if you have any problems.

 

Cheers,

 

Peter (pjv)

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