In SX Microcontrollers, SX/B Compiler and SX-Key Tool, Peter Van der Zee wrote:

Hi Andrew;

Still I think you are incorrect....... I like to work on the basis where we do not have control over the sender, and we have to live with whatever we get, provided it's "in-spec".

There is absolutely no problem in sampling only once (in the middle) of each bit, PROVIDED that we "see" the front edge of the start bit sufficiently rapidly. My experience is (and that is considerable) that one can "get away" with 3X over sampling, but 5X is more "comfortable". If one does the latter, there will never be a problem with bit-drift. If one does the former, one is generally OK.

But "generally" isn't good enough, as I like to design things so they ALWAYS work as long as things (timing) are in-spec. So to deal with this, I wrote a VP UART that oversmples 3X, and then also adjusts its synchronization on any transition it sees along the way in receiving the byte. It works, absolutely, 100% of the time.

I'm not suggesting that's what James requires here, as his problem is sampling at inconsistent times. A temporary shadow register will solve that for him, and I guarantee you it will work 100% without messing with the sender.

If the sender is out of spec of course, that's a different story.

By the way James, I don't know if I'll get this done for you tonight........more likely some time this weekend.

Cheers,

Peter (pjv)

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