In SX Microcontrollers, SX/B Compiler and SX-Key Tool, amiller wrote:

Peter,

If the stop-bit length is 1/bitrate, as expected, the VP will still accumulate the error.  Basically, the VP can't see the "edge" of the start-bit until after the error-accumulated stop-bit time, pushing the start-bit's "window" further and further out of sync.  

If your receiving VP isn't waiting for the whole stop-bit, then yes, you are correct. That is not the poster's case.  

Most/All of the existing SX UART VP's around just take one sample in the middle of the bit period.  This is simpler/smaller code, and works, until the bit timing accumulates a (bittime/2) error, pushing the sample point past one end (start or finish) of the real bit period.

I once started work on a smarter UART VP, one that looks at several bit samples within a bit's period to determine the sent bit's value.  I abandoned the project when the ISR code grew too long for the project, instead making sure the sender paused between large blocks of data to reset bit timing and re-find the leading edge of the start-bit.

-AGM

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