In SX Microcontrollers, SX/B Compiler and SX-Key Tool, Peter Van der Zee wrote:

Hi James;

I think you are correct in your assessment; although I have not attempted to run your code.

Does the problem go away when you run at slower baud rates?  If so, then that is more evidence of your suspicions.

What you are doing in your ISR, is sampling the inputs, and setting the outputs at somewhat indeterminate times (instruction cycle wise) due to the unpredictability of which UART (1 or 2) and which element (transmit or receive) is doing what. And that is an external, unpredictable affair.

You could fix that by sampling the UART inputs into a temporary storage at a fixed point near (at ?) the beginning of your ISR, and also set the UARToutputs from a temporary (shadow) register at a fixed point in your ISR. What is important is the time from entering the ISR and the point where you sample the inputs and set the outputs be always at the same time (hence instruction) reference.

This is most easily accomplished by having no variable instruction paths prior to these events, and that is done with temporary shadow registers.

Other than that, I believe your code can also be "tightened up" by 20% to 40%, and I'd be happy to have a go at that if it's of (significant) interest to you. (I live for the challenge, you see, but do not want to waste my time).

I assume you will always transmit (relay) the received data at the same data rate? In other words 115200 in to 115200 out, and both in 8N1 format.

Please advise.

Cheers,

Peter (pjv)

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