In SX Microcontrollers, SX/B Compiler and SX-Key Tool, ShadowsSoldier wrote:

Here is my modified code. The problem I have identified still mystifies me. In short, depending on the value of TX1TX2 (0000_0000 or 1111_1111) the IRC rountine takes one of two paths. In one path the cycle count in the SXSim is always 64 (what I need) in the other path it is always 63 (when TxT1 is set to 1111_1111). Each path when selected will repeat for a total of six interupts - so I don;t see why there is a discrepancy. Does anyone else see what I am saying?

BBAL

;5.120 MHz version 

Device SX28L, Turbo, Stackx, OSCHS3
IRC_CAL IRC_SLOW
FREQ	5_120_000


RESET ResetEntry 

ORG 0					

Interrupt	 				; Interrupt Routine - always starts at 0
DEC CycleCount	    			        ; countdown to 255
JNB CycleCount.7, WRITE				; cyclecount.7 = 0, compare
;----------------------------------------------------------------------------
						; underflow occurs, reconfigure IRC
		Setb Recon.0			; Recon to TRUE
Exit		JNB IRCState.0, TermPSA
TermRTCC	Mov w, #-64
Go		Retiw				; single exit point
TermPSA		Mov w, #-%1111111
		JMP Go			
;----------------------------------------------------------------------------

WRITE		JNB IRCState.0, TermPSA		; jump to prescaler return if IRCState=0  
		JNB TX1TX2.0, WriteRa 		; toggle a port during RTCC - but which?
		NOT output1			
		Mov w, output1
		Mov Rb, W			; write RB
		JMP TermRTCC			; terminate write RB	
WriteRa		NOT output2
		Mov w, output2			
		Mov Ra, w			; write RA
		JMP TermRTCC			; terminate write RA



Org 08


CycleCount		ds 1	
TX1TX2			ds 1
IRCState		ds 1
IRCRecon		ds 1
Output1			ds 1
Output2 		ds 1
Recon			ds 1



Org 100

ResetEntry

;load predefined registers

	Clr Cyclecount			; trigger var
	Clr TX1TX2			; Tx1/Tx2 (0/1)
	Clr IRCState			; 0 = RTCC w/ PSA , 1 = RTCC 
 	Clr Recon			; 0 = don't reconfigure, 1 = reconfigure
	Clr Output1			; toggle state TX1
	Clr Output2			; toggle state TX2

; de-glitch initial state

	Mov w, #%0000
	Mov Ra, w		; set register A output to digital LOW
	Mov w, #%0000_0000	
	Mov Rb, w		; set register B output to digital LOW
	Mov w, #%0000_0000
	Mov Rc, w		; set register C output to digital LOW

; configure ports

	Mov M, #$0f		; access TRIS mode
	Mov W, #%0000		; bits 0-3 are outputs
	Mov !Ra, W		; make Ra0-Ra3 outputs	
	Mov W, #%0000_0000	; all bits output
	Mov !Rb, W		; set Port B pins to output
	Mov W, #%0000_0000	; all bits output
	Mov !Rc, w		; set Port C pins to output


	
; Initialize
	
	Not TX1TX2				; select TX 1/2 toggle this on and off and you get a 63-64 cycle difference
	Not Recon				; toggle reconfigure
	
Start

JNB Recon.0, Loop					; if recon = FALSE do not reconfig
Call Reconfigure

Loop
JMP Loop


; Subroutine
Reconfigure
		NOT IRCState			; flip state
		JNB IRCState.0, PSA
		Mov w, #%1100_0000 		; initialize RTCC = 191  
		Mov rtcc, w		
		Mov w, #%1001_1111		; reconfigure as RTCC only! 
		Mov !option, w
		Mov w, #%0000_0110		;  
		Mov CycleCount,w		; set cyclecount to 6 (bit 7 ON on underflow)- 64 cycles = 12.5 us
		NOT TX1TX2			; flip transmitter select 
		JMP EndRoutine				; configuration complete
PSA		Mov w, #%0000_0001
		Mov RTCC, w			; initialize RTCC to 0	
		Mov w, #%1000_0001		; reconfigure RTCC with PSA 1:4
		Mov !option, w
		Mov w, #%0000_0001		; Mov w, #%0001_0100
		Mov Cyclecount, w		; set counter to 20 (bit 7 ON on underflow)- 20 cycles prescaled = 4.0 ms
		Mov w, #-%1111111		; jump ahead to call IRC every 256 cycles
EndRoutine	Clrb Recon.0			; set reconfigure to false
		Ret

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