In SX Microcontrollers, SX/B Compiler and SX-Key Tool, ShadowsSoldier wrote:

Hi folks, I am having trouble understanding why one of my interrupt routines is going at every 62 or 63 cycles instead of every 64. When I don't use conditional instructions such as JNB and break it out from the rest of the program in a new one, it hits every 64 cycles like a charm. I thought the mov w, #-64 and then retiw took care of this but I am still coming up a few cycles short in my program below. Just to give you background on what this code does is that it dynamically reconfigures the IRC to switch back and forth betwen 40KHz and 250Hz while alternating the output between two different pins every time 40KHz occurs. It works ok, I just don't understand the small descrepancy in cycles.

FYI the intital state is set to run the 40 KHz first. The routine is contained in the IRC under :RTCC and also the first configuration of the RTCC. Sorry about the uneven indents and stuff. Thats not how it looks in my editor though.


Thanks to anyone that can help.


Device SX28L, Turbo, Stackx, OSCHS3
IRC_CAL IRC_SLOW
FREQ	5_120_000


RESET Start 

ORG $000						

Interrupt	 				      ; Interrupt Routine - always starts at $00
DEC CycleCount	    			        ; countdown to 255
JNB CycleCount.7, WRITE			    ; cyclecount.7 = 0, toggle? go to accessment
;----------------------------------------------------------------------------
						          ; underflow occurs, reconfigure IRC
NOT IRCState					  ; flip state
JNB IRCState.0, :RTCCPSA
:RTCC		Mov w, #%1100_0000		; initialize RTCC = 191
		Mov rtcc, w		
		Mov w, #%1001_1111		    ; reconfigure as RTCC only! 
		Mov !option, w
		Mov w, #%0000_0110		;  
		Mov CycleCount,w		    ; set cyclecount to 6 (bit 7 ON on underflow)- 64 cycles = 12.5 us
		NOT TX1TX2			      ; flip transmitter select 
      		reti				             ; configuration complete
:RTCCPSA	Mov w, #%0000_0001
		Mov RTCC, w			      ; initialize RTCC to 1
		Mov w, #%1000_0001		; reconfigure RTCC with PSA 1:4
		Mov !option, w
		Mov w, #%0001_0100
		Mov Cyclecount, w		; set counter to 20 (bit 7 ON on underflow)- 20 cycles prescaled = 4.0 ms
		reti	
;----------------------------------------------------------------------------
WRITE		JNB IRCState.0, RetRTCCPSA	; jump to prescaler return if IRCState=0  
		JNB TX1TX2.1, :Ra 		; toggle a port during RTCC - but which?
		NOT RB				; write RB
		JMP RetRTCC	
:Ra		NOT RA				; write RA
RetRTCC		Mov w, #-64
		Retiw
RetRTCCPSA	Retiw

Org $08


CycleCount		ds 1	
TX1TX2			ds 1
IRCState		ds 1
IRCRecon		ds 1

Org $100

Start

;load predefined registers

	Clr Cyclecount			; trigger var
	Clr TX1TX2			; Tx1/Tx2 (0/1)
	Clr IRCState			; 0 = RTCC w/ PSA , 1 = RTCC 
 	Clr IRCRecon

; de-glitch initial state

	Mov w, #%0000
	Mov Ra, w		; set register A output to digital LOW
	Mov w, #%0000_0000	
	Mov Rb, w		; set register B output to digital LOW
	Mov w, #%0000_0000
	Mov Rc, w		; set register C output to digital LOW

; configure ports

	Mov M, #$0f		; access TRIS mode
	Mov W, #%0000		; bits 0-3 are outputs
	Mov !Ra, W		; make Ra0-Ra3 outputs	
	Mov W, #%0000_0000	; all bits output
	Mov !Rb, W		; set Port B pins to output
	Mov W, #%0000_0000	; all bits output
	Mov !Rc, w		; set Port C pins to output

; set intial conditions

	
	Not TX1TX2				; select TX1 (indirect)
	Not IRCState
	JNB IRCState.0, :RTCCPSA
:RTCC		Mov w, #%1011_1111		; initialize RTCC = 191
		Mov rtcc, w		
		Mov w, #%1001_1111		; reconfigure as RTCC only! 
		Mov !option, w
		Mov w, #%0000_0110		;  
		Mov CycleCount,w		; set cyclecount to 6 (bit 7 ON on underflow)
		JMP Main 

:RTCCPSA	Mov w, #%0000_0001
		Mov RTCC, w			; initialize RTCC to 0	
		Mov w, #%1000_0001		; reconfigure RTCC with PSA 1:4
		Mov !option, w
		Mov w, #%0000_0000
		Mov Cyclecount, w		;

MAIN

JMP Main

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