In SX Microcontrollers, SX/B Compiler and SX-Key Tool, peterverkaik wrote:

Hi pjv,
The mainlevel code can only be interrupted by the sx isr routine, which has limited instruction
cycles (in my example program 217). What I do is create a new mainlevel isr that is
executed every N'th sx isr cycle. This mainlevel isr executes as mainlevel code (and thus gets
interrupted by the sx isr) but it appears as an interrupt routine to the mainloop code.
This mainlevel isr can have more instruction cycles than the sx isr routine.
So I don't have multiple threads, but still only one thread, but with an interrupt routine
that can be larger. It is intended for lower frequency events like postprocessing
serial receive events, scheduled timer events etc. It is not intended as a tight realtime design,
unlike your RTOS. I got this idea after studying an old MSX BIOS listing (home computer mid 80's)
where there is an interrupt cycle every 20 millisecs in which a complete keyboard was scanned,
several uarts were processed and some other checks. For my applications, that mostly involve
uarts, this approach may work well, without the overhead of saving context for preemptive
threads (the mainlevel isr, being an interrupt routine by definition, must always completes its code and has
no context that must be saved).
I hope this clarifies what I had in mind.

BTW, can I have a view on your rewritten RTOS? 
regards peter

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