In SX Microcontrollers, SX/B Compiler and SX-Key Tool, Chong wrote:

Hi Bean,

The $FF load is an anachronism when I thought loading $00 would re-enable interrupts prematurely. I had thought that loading $00 would allow an interruption of my ISR. I now realize that the RETI enables interrupts again. However, the $FF load is to swap the interrupt cause into W to affect how my ISR responds to one of two sources of interrupt.

I did not know that an interrupt while the ISR was running would que up a subsequent interrupt. Perhaps my strange running is associated to that somehow. 

I'm not sure how as adding in the SETB instruction at the end shouldn't affect the flow of my code much as the SETB is to an output pin. I'm baffled why the write to RB has to be at the end of my ISR. If I enable the RB writes at the beginning but comment out the writes at the end, I have different program flow than when the writes are put at the end.

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