> I seem to remember a discussion somewhere (maybe on the Microchip
> forum) about whether any of the PICs had an atomic test and set
> capability.  The consensus seemed to be that this was not possible.
> 
> Olin, do you know if this is correct? I think it's possible, e.g. on
> an 18F, if you use only high priority interrupts, but I'm not sure
> whether this covers every situation, such as low power or brownout
> conditions.

I don't see the use of a test-and-set on 12 and 14 bit cores:
test-and-set is used to implement a semaphore, which is usefull only in
the context of pre-emption. 

But if you want the effect of a test-and-set I think there is a
two-instruction sequence that could be used within reasonable
limitations (like: not too many running processes - and you can't have
more than 2 or 3 anyway - main + 1 or 2 interrupts). I leave it as an
excercise to the reader to find such a sequence :)

Side note: for embedded systems the attractiveness of preemption is not
timeslicing but responding to events (most important: timeouts).

Wouter van Ooijen

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Van Ooijen Technische Informatica: www.voti.nl
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