On 1/20/06, Gerhard Fiedler wrote: > > Shawn Wilton wrote: > > > Which uC are you using? > > This device is using one of the 18F6722 family. But this is not really > relevant because the built-in EEPROMs seem to be pretty much the same WRT > endurance. Yeah, I was asking because the 18F452 for example, has only 256B of memory. > The (for example) pic18f452 specifies a read/write cycle of 1E6. Not > > bad! > > I suppose you're looking at D124, and forgetting about D120? Or you're > looking at the typical value and not counting the minimum value? FWIW, I > was looking at the minimum value for D120, and this is 100k for my chip > and > the 18F452. True. Looked it over and yes, 1E5 cycles typical. Was only glancing at the front page. Seems a bit misleading.. > So upgrade your chip and maybe you can run your device until dogs really > > do run over the world... > > Doesn't look like this would be an upgrade :) > > > Doing some hunting around in various data sheets, I do believe I have > > answered my own question regarding EEPROM size (256B?). > > In the chip in the device I'm using it's 1k. In that case, using circular buffers, you could in theory achieve around 50M events Gerhard > > -- > http://www.piclist.com PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist > -- Shawn Wilton (b9 Systems) http://black9.com -- http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist