Ian Chapman wrote:
> My understanding from this is that there is no mechanism in the
> PIC16F818 hardware for the slave to delay the master in sending a stop
> condition at the end of a transmission.

Right.  The basic MSSP in the PIC 16 only does clock stretching as slave on
a read, not on a write.  This unfortunately means there is no good way to do
flow control in one direction.

> My code drives a port pin low on entry to the ISR (immediately after
> saving context) and before it carries out any actions on SSPSTAT, SSPIF
> etc.  The logic analyser trace shows this bit going low 1-2 instruction
> cycles after the stop condition on the I2C bus.

OK, that means you're rather slow about getting into the interrupt, but why
is this an issue?

> There seems to be no
> automatic action taken by the slave to delay this stop condition.

Right, but why would you want to?

> I guess another possibility is that the SSP module is supposed to latch
> the state of the S bit so that it can be read as a one by the ISR even
> after a stop condition has reset its real-time state to a zero.
> However, I haven't seen any reference to this in the data sheet and,
> even if it does occur, I don't see how my code could cause the state of
> the latch to be lost.  The only action that my ISR takes in relation to
> the SSP module before reading SSPSTAT is to clear the SSPIF interrupt
> flag after checking that it is set. I might try a quick test with the
> clear of SSPIF after the read of SSPSTAT, but I don't expect it to make
> a difference.

It sounds like everything is working as intended.  What exactly is the
problem?  Can you describe it in plain english without references to an AN
or things that require looking in the manual like finding out what the "S"
bit is?


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