> I'm using the internal EEPROM of a PIC (that's why I used the
> PIC tag :)

Ah, I wondered why I had the impression you weren't and looked
at the original post. You'd said "Microchip's EEPROMs have 100k
write cycles endurance spec'ed" and I think I drew the conclusion
this was an external. But that's OK, no big whoop, just a misunder-
standing

> and I'm not aware of page or block modes for these devices

AFAIK all PICs except the 30F have single-byte EEPROM access

The only block operation I know of in not-30F is the block write
to Flash

> Anyway, with an external EEPROM, would this mean that if you
> write only complete blocks, you get a higher endurance? OTOH,
> there are more cells you're writing to; does this increase the
> probability of failure? I'm not quite clear about the mechanisms here

It's explained in AN601 -

"The charge pump voltage is used to program however
many EEPROM-cells are being programmed. For
example, in byte mode, all the cells in a byte (8 to 16)
are biased with the charge pump voltage. In block
mode, all the cells in the array (up to 100,000,
depending on the device) are biased with the charge
pump voltage. The charge pump is like a current
source during conditions of high load, so the voltage
put out by the charge pump will be reduced slightly if
more bytes are being written. If the whole array is being
programmed then the charge pump voltage will be
significantly reduced, but the programming current Ipp
will be very high

Generally, the lower the charge pump voltage the
better the endurance......."

> It sure sounds like this. Sounds like it was a good idea to run
> EEPROMs on as low a Vdd as you can

On re-reading the AN, and if I were in your situation, I think
I might try lowering Vdd just for EEPROM writes (unless
you didn't need 5V Vdd at any time, in which case run the
PIC with a permanent low Vdd anyway)

There's also the PIC's Flash memory don't forget. It's not
as high endurance, but there could be a lot of it sitting idle

I might prefer doing all the logging in RAM and writing
periodically to EEPROM, rather than using EEPROM for
every single event. And having the power-fail system for
not losing RAM data

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