Which uC are you using?  The (for example) pic18f452 specifies a read/write
cycle of 1E6.  Not bad!  So upgrade your chip and maybe you can run your
device until dogs really do run over the world...

Doing some hunting around in various data sheets, I do believe I have
answered my own question regarding EEPROM size (256B?).

On 1/19/06, Gerhard Fiedler <lists@connectionbrazil.com> wrote:
>
> Jinx wrote:
>
> > http://home.clear.net.nz/pages/joecolquitt/Mchip00601.pdf  (70kB)
> > http://home.clear.net.nz/pages/joecolquitt/Mchip00602.pdf  (60kB)
> >
> > "Write Modes In EEPROMs" in AN601 is interesting
> >
> > "A general rule to follow in choosing write modes is that the larger the
> > number of bytes being written in a single instruction, the longer the
> > device will last. For example, in byte mode a device might start to fail
> > after 300,000 cycles under a particular set of conditions, but the
> > device may last 600,000 cycles in page mode under the same conditions.
> > In block mode the device might last 1 million cycles, under the same
> > conditions"
>
> I'm using the internal EEPROM of a PIC (that's why I used the PIC tag :),
> and I'm not aware of page or block modes for these devices.
>
> Anyway, with an external EEPROM, would this mean that if you write only
> complete blocks, you get a higher endurance? OTOH, there are more cells
> you're writing to; does this increase the probability of failure? I'm not
> quite clear about the mechanisms here.
>
> > "Generally, the lower the charge pump voltage the better the endurance
> > (there is a limit since the charge pump voltage needs to be high enough
> > to program the cell) ........."
> >
> > I wonder then, if you drop Vdd (easy enough to do with a
> > resistance-controlled regulator) before writing to EEPROM, you'd up the
> > endurance ???
>
> It sure sounds like this. Sounds like it was a good idea to run EEPROMs on
> as low a Vdd as you can.
>
> Gerhard
>
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Shawn Wilton (b9 Systems)
http://black9.com
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