>I assume that AN734 was developed on a PIC running at,
>say, 20MHz with no foreground interrupt latency and,
>perhaps, a slower I2C bus speed, in which case this
>timing issue would never occur.

I don't believe this. There must be something strange in your code.

I haven't gone digging in the code to check, but IIRC the I2C bus hangs up
until the receiving device releases the clock line to signal the ACK/NAK.
This is done in code on the PIC, so any interrupt latency just appears as a
delay in releasing the clock line. Hence the S bit should still show the
correct state until you release the clock line in the code.

I ran the code on a 16F876 at 3.6864MHz clock with absolutely no glitches
like you describe, so I have no reason to believe it was developed on a
faster chip, with the consequences you suggest.

-- 
http://www.piclist.com PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist